Capacitive node isolation for electrostatic discharge circuit

ABSTRACT

Capacitive node isolation circuitry in an integrated circuit eliminates the creation of hot spots (stored charge) on high capacitive nodes during a test of electrostatic discharge (ESD) protection circuitry of the integrated circuit or during any ESD event occurring while the integrated circuit is in a standby mode. The isolation circuitry includes a standby mode logic circuit responsive to a standby mode signal received at one of its inputs and provides an output signal to a gate of an active switching device located in a path between an external pin of the integrated circuit and the internal high capacitive node. The output signal keeps the active switching device turned off for the duration of the ESD test or ESD event. The standby mode logic circuit transparently passes an input logic signal to the active switching device whenever the integrated circuit is in a normal operating mode.

TECHNICAL FIELD

The present invention relates to integrated circuit testing and inparticular relates to improvement of electrostatic dischargecapabilities of integrated circuits.

BACKGROUND ART

Integrated circuits are typically provided with electrostatic discharge(ESD) protection circuitry between the external pins of the device andthe main circuit in order to shunt ESD pulses safely to ground andthereby prevent damage to the integrated circuit. Typical ESD pulses caneasily exceed 2000 Volts and deliver peak currents of 1 to 30 Ampereswithin a rapid rise time of 1 to 10 nanoseconds followed by a slow decayin electrical current over the next 100 nanoseconds or so. As a normalpart of quality control following integrated circuit manufacture, theESD protection circuitry is tested. An ESD test normally involvesapplying a standard electrical waveform representative of one or moreESD events to the various external pins of the manufactured device andobserving whether or not the ESD protection circuitry associated witheach of those pins adequately handles the test waveform within specifiedtolerances.

Unfortunately, it has been observed that, notwithstanding the presenceof ESD protection circuitry manufactured to design specifications, thevery act of ESD testing can, under certain circumstances, createdamaging hot spots (stored charge) within an integrated circuit. This isparticularly the case when the power supply pin is being tested. Thepower supply pin is connected to many circuit elements in the maincircuit in order to provide the electric power needed for its normaloperation. Integrated circuits may also include large capacitive nodes(long conductive lines), which can be coupled through such circuitelements to the power supply pin.

For example, FIG. 1 shows a typical CMOS inverter comprising p-channeland n-channel transistors P1 and N1. The p-channel transistor P1 of thisinverter is connected to the power supply (VCC) pin. A conductive line 5forms a high capacitance node B at the output of this inverter.Accordingly, in this circuit the high capacitive node B is coupled tothe VCC pin by the transistor P1. For an ESD test of the VCC pin, thechip is placed in a standby mode. However, this may not guarantee thatthe transistor P1 will remain of during an ESD test. If node A on theinput side of the inverter happens to be at a logic 0 voltage level whenthe chip enters standby, then the p-channel transistor P1 could turn onwhen the VCC pin momentarily goes high during an ESD test pulse. Thatwill in turn couple the VCC pin to the high capacitive node B, which maythereby receive charge from the ESD test pulse via that VCC pin. Thisreceiving of charge may occur even though most of the charge is safelyshunted to ground by the ESD protection circuitry associated with theVCC pin, and in some cases the amount of charge received by a highcapacitive node B can be quite large. After the ESD test, when the powersupply voltage has gone back down, the transistor P1 shuts off,isolating the high capacitive node B and its stored charge. N-channeltransistor N1 remains off through the entire test operation and thusdoes not provide a sink to ground for the charge received and stored atnode B. The high capacitive node B discharges only very slowly.

Although the amount of stored charge and its associated voltage is notlarge enough to immediately damage the devices connected to the highcapacitive node—that after all is the main reason for having ESDprotection circuitry—if a high voltage at node B were to be sustainedfor a long enough time, it could stress the connected devices such thatjunction degradation in those devices is possible. Current leakageresulting from junction degradation of any devices can cause circuitmalfunction under normal operation.

SUMMARY DISCLOSURE

The present invention eliminates the ESD charge storage problem on highcapacitive nodes coupled to an external pin. In particular, theintegrated circuit is provided with a logic circuit element, such as alogic gate, responsive to a standby mode signal for generating a controlsignal that is applied to the gate of a transistor or other activeswitching element between the external pin and a high capacitive node inorder to ensure that in a standby mode, the transistor or activeswitching element remains off during an ESD test, or during theoccurrence of an ESD event, so that the external pin is effectivelyisolated from the high capacitive node during such ESD test or event.Such a logic circuit element is included at every location in theintegrated circuit where a high capacitive node could potentiallycoupled to an external pin. The added logic circuit element is chosen tobe transparent whenever the integrated circuit is not in a standby mode.

Alternatively or in addition, and wherever possible, the high capacitivenode could be broken into many smaller capacitive nodes with duplicatedrivers or other active circuit devices connected to the several smallercapacitive nodes in order to eliminate or reduce to a minimum the numberof high capacitive nodes needing standby isolation for the ESD test.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic circuit diagram of a prior art inverter circuitcoupled to both a power supply pin and a high capacitive node.

FIG. 2 is a schematic circuit diagram of an exemplary embodiment of thepresent invention providing a standby mode logic circuit (here, a NANDgate) coupled to the input end of an inverter circuit associated with ahigh capacitive node.

FIG. 3 is a schematic circuit diagram of an alternative or additionalembodiment of the present invention, illustrating the break-up of a highcapacitive node into plural smaller capacitive nodes, each with its ownassociated inverter driver.

DETAILED DESCRIPTION

With reference to FIG. 2, a high capacitive node B can be coupled, forexample, to a power supply pin VCC via an active switching element of anintegrated circuit, e.g., in this embodiment, a p-channel transistor P2of a CMOS inverter. Likewise, in this exemplary embodiment, the node Bcan also be coupled to ground pin of the integrated circuit via anotheractive switching element of the circuit, namely an n-channel transistorN2 of the CMOS inverter. When the inverter's input A′ is at a logic 0level, the p-channel transistor P2 will be on, coupling the VCC pin tothe node B, while the n-channel transistor N2 will be off, isolating thenode B from ground. Node B will be pulled up to the VCC voltage level.In contrast, when the inverter's input A′ is at a logic 1 level, thep-channel transistor P2 will be off, so that node B is isolated from theVCC pin, while n-channel transistor N2 will be on, coupling the node Bto ground. The inverter shown here is merely exemplary of a circuitelement coupling a high capacitive node B to an external device pin viaan active switching device, such as the transistor P2. The external pinneed not be a power supply pin VCC. A variety of other circuit elements,such as NAND and NOR logic gates, latches and flip-flops, amplifiers,etc., also have switching elements that can couple a high capacitivenode to the pin. In addition to the switching device, such as transistorP2, there may be additional resistive or capacitive elements present inthe path between the external pin and the internal pin and the internalhigh capacitive node B that still permit coupling between the pin andnode. The present invention encompasses all of these cases and providesthe additional logic circuitry that ensures that high capacitive nodes,like node B, remain isolated from the external pin during a standbymode. The integrated circuit would be placed in the standby mode for anESD test on a pin. The invention's isolation of the high capacitive nodefrom the external pins of the device present any charge from an ESDevent reaching the internal node.

In FIG. 2, the additional logic circuitry is in the form of a NORgate-inverter combination 11 and 13 that generates a control signal atthe node A′ which is guaranteed to keep transistor P2 off in a standbymode, while transparently passing a logic signal A to the affectedcircuit elements P2 and N2 in a normal operating mode. As already noted,the transistor P2, between the VCC pin and high capacitive node B, isoff when the input node A′ gating the transistor P2 is at a logic 1level. Accordingly, the NOR gate-inverter combination 11 and 13 is usedto provide a logic 1 level in the standby mode. The NOR gate 11 receivesa logic signal A and also a STANDBY mode signal at its respectiveinputs. During a standby mode (STANDBY=1), the output A′=1 from the NORgate-inverter combination 11 and 13. During a normal operating mode(STANDBY=0), the signal A′=A, and thus the additional logic circuitry 11and 13 is completely transparent for the logic signal A.

Depending on the particular circuitry coupling a high capacitive node tothe VCC pin, and in particular the type of active switching device(p-channel versus n-channel transistor) located between the VCC pin andthat high capacitive node, the inverting element 13 may not be needed.In particular, if an n-channel transistor were to couple a highcapacitive node to the VCC pin, then a logic 0 input to thattransistor's gate would be needed during standby to guarantee theisolation of the node from the VCC pin.

The polarity of the STANDBY mode signal can be reversed (STANDBY=0during standby mode, =1 during normal operation), in which case the NORgate 11 can be replaced with a NAND gate.

Note also, that in addition to isolating the node B from the VCC pin,the additional circuitry's signal output also guarantees that thetransistor N2 to ground is on, providing a current sink for the node B.

The additional circuitry is provided in the integrated circuit onlywhere high capacitive nodes are present that could form hot spots duringen ESD test. Exactly what constitutes a “high” node capacitance is adesign parameter that depends, for example, upon the capabilities of theESD protection circuitry provided with the integrated circuit, theconductance properties of the active switching device coupling the nodeto the VCC pin, the desired stress limits upon devices coupled to thatnode. A circuit designer can provide the additional logic circuitrywhenever it is determined that a particular node meets a specified“high” capacitance condition.

With reference to FIG. 3, in an alternative or additional embodiment,some or all of the nodes in an integrated circuit that are determined tobe high capacitance nodes can be divided into several smallercapacitance nodes, e.g., nodes B1, B2 and B3. Each of these smallercapacitance nodes would require their own drivers, such as the inverters22, 23 and 24 for nodes B1, B2 and B3. Between the input 21 receiving alogic signal A and the output 25, the multiple drivers and nodes arefunctionally equivalent to a single driver and high capacitance node,but the specified high capacitance condition is not met by any of thesmaller capacitance nodes B1, B2 or B3. Thus, the additional logic inFIG. 2, such as the NOR gate-inverter combination 11 and 13 would not beneeded in that case. Alternatively, if a particular node has a very highcapacitance, that node could be divided into smaller high capacitancenodes that would still require the additional logic 11 and 13, but thesubdividing into smaller capacitances would provide additionalassurances that the associated devices coupled to the respective nodesB1, B2 and B3 would not be unduly stressed in the event some charge weresomehow to couple into one or more of those nodes.

An integrated circuit according to the present invention may have nodesthat are provided with either or both of the solutions described usingthe examples in FIGS. 2 and 3, including some nodes having theadditional circuitry 11 and 13 of FIG. 2, other nodes subdivided as inFIG. 3, and possibly still other nodes being both subdivided andprovided with the additional logic.

1. Capacitive node isolation circuitry in an integrated circuit subjectto an electrostatic discharge (ESD) test or ESD event, the capacitivenode isolation circuitry comprising: an active switching device in apath coupling a node in the integrated circuit to an external pin, thenode meeting a specified high capacitance condition, and a standby modelogic circuit having a first input coupled to receive an input logicsignal, a second input coupled to receive a standby mode signal, and anoutput coupled to provide a signal to a control gate of the activeswitching device, such that whenever the standby mode signal is at afirst signal level indicating normal operation of the integratedcircuit, the input logic signal is provided as the output signal of thestandby mode logic circuit, but whenever the standby mode signal is at asecond signal level indicating a standby mode of the integrated circuit,the standby mode logic circuit provides an output signal that causes theactive switching device to be off, thereby actively isolating the nodefrom the pin in the standby mode.
 2. The capacitive node isolationcircuitry as in claim 1, wherein the active switching device is an MOStransistor.
 3. The capacitive node isolation circuitry as in claim 2,wherein the MOS transistor is a p-channel transistor and the outputsignal from the standby mode logic circuit has a logic 1 level in thestandby mode.
 4. The capacitive node isolation circuitry as in claim 2,wherein the MOS transistor is an n-channel transistor and the outputsignal from the standby mode logic circuit has a logic 0 level in thestandby mode.
 5. The capacitive node isolation circuitry as in claim 1,wherein active switching device is a component of a logic circuitelement of the integrated circuit.
 6. The capacitive node isolationcircuitry as in claim 5, wherein the logic circuit element with theactive switching device also comprises at least one other activeswitching device connecting the node to a ground pin, said other activeswitching device also responsive to the output signal from the standbymode logic circuit to turn on during the standby mode.
 7. The capacitivenode isolation circuitry as in claim 1, wherein the second signal levelof the standby mode signal indicating a standby mode is a logic 1 level,the standby mode logic circuit comprising a NOR gate with two inputs ofthe NOR gate forming the first and second inputs to receive therespective input logic signal and standby mode signal.
 8. The capacitivenode isolation circuitry as in claim 7, wherein the standby mode logiccircuit further comprises an inverter connected in series to an outputof the NOR gate, such that an output of the inverter provides the outputsignal of the standby mode logic circuit, the output signal having alogic 1 level in the standby mode.
 9. The capacitive node isolationcircuitry as in claim 1, wherein the second signal level of the standbymode signal indicating a standby mode is a logic 0 level, the standbymode logic circuit comprising a NAND gate with two inputs of the NANDgate forming the first and second inputs to receive the respective inputlogic signal and standby mode signal.
 10. The capacitive node isolationcircuitry as in claim 9, wherein the standby mode logic circuit furthercomprises an inverter connected in series to an output of the NAND gate,such that an output of the inverter provides the output signal of thestandby mode logic circuit.
 11. A method of isolating a capacitive nodein an integrated circuit from an external pin during an electrostaticdischarge (ESD) test or ESD event, the method comprising: placing theintegrated circuit in a standby mode, including asserting a standby modesignal, the standby mode logic signal being received by a standby modelogic circuit associated with an active switching device in a path thatcouples a node in the integrated circuit to an external pin, the nodemeeting a specified high capacitance condition; and generating an outputsignal in the standby mode logic circuit and providing said outputsignal to a control gate of the active switching device with a signallevel that causes the active switching device to be off, therebyactively isolating the node from the pin in the standby mode.
 12. Themethod as in claim 11, further comprising: conducting an electrostaticdischarge (ESD) test while the integrated circuit is in the standbymode; at any time after the conclusion of the ESD test, placing theintegrated circuit in a normal operating mode, including de-assertingthe standby mode signal; and transparently passing an input logic signalthrough the standby mode logic circuit to provide an output signal tothe active switching device that corresponds to the input logic signal.